1. Field of the Invention
Embodiments relate to a semiconductor memory device. More particularly, embodiments relate to a flash memory device storing multi-bit data and associated methods.
2. Description of the Related Art
A flash memory device is a type of an electrically erasable programmable read-only memory (EEPROM) in which a plurality of memory regions, i.e., a memory block, are erased or programmed by one program operation. The simultaneous operations allow the flash memory device to operate effectively at high speed.
The flash memory device is a non-volatile memory device, i.e., does not require power to retain stored information, is resistant to physical impact, and provides fast read access times. Due to these properties, the flash memory device is extensively used in battery powered devices.
Flash memory devices may be classified as a NOR flash memory device and a NAND flash memory device according to a logic gate used. Typically, flash memory devices store information on an array of transistors, called a cell. In a single level cell (SLC) flash memory, each cell stores 1 bit of data. Newer flash memory devices, called multi-level cell (MLC) flash memories, allow more than 1 bit to be stored in each cell, e.g., by changing an amount of electric charges on a floating gate of a cell.
FIG. 1 illustrates a block diagram of a typical NAND flash memory device. As illustrated in FIG. 1, the NAND flash memory device includes a memory cell array 10, a row selector (hereinafter, referred to as an x-selector) 20, and a data register and sense amplifier (S/A) 30. The memory cell array 10 includes a plurality of memory blocks MB0 to MB(m−1). Each of the memory blocks MB0 to MB(m−1) may store 2N-bit data (N is a positive integer equal to one or above). In response to a row address, the x-selector 20 selects one of the memory blocks MB0 to MB(m−1) and one of word lines in the selected memory block. The data register and S/A 30 is connected to the selected memory block through a bit line, and operates as a write driver while performing a program operation and as a sense amplifier while performing a read operation.
FIG. 2 illustrates a block diagram of a portion of a memory block MB0 in a flash memory and the data register and S/A 30. Referring to FIG. 2, the memory block MB0 may include strings 11 connected to a plurality of bit lines BLe0, BLo0, BLe1, BLo1, . . . , respectively. Each of the strings 11 may include a string select transistor SST, a ground select transistor GST, and memory cells MC31 to MC0 connected in series between the string select transistor SST and the ground select transistor GST. The string select transistors SST in the strings 11 may be commonly connected to the string select line SSL controlled by the x-selector 20 of FIG. 1. The ground select transistors GST in the strings 11 may be commonly connected to the ground select line GSL controlled by the x-selector 20 of FIG. 1. The memory cells MC31 to MC0 in each string 11 may be respectively connected to corresponding word lines WL31 to WL0 controlled by the x-selector 20 of FIG. 1. For convenient description, a pair of bit lines BLe0 and BLo0 is illustrated in FIG. 3. Remaining memory blocks MB1 to MB (m−1) substantially have the same structure as the memory block MB0 illustrated in FIG. 2, and their descriptions will be omitted for convenience.
The data register and S/A 30 may include a bit line selector 31 and a register 32 connected to the pair of bit lines BLe0 and BLo0. The bit line selector 31 may select one of the pair of bit lines BLe0 and BLo0, and may electrically connect the selected bit line with the register 32. During a program operation, the register 32 may supply the selected bit line with a program voltage (e.g., a ground voltage) or a program prohibit voltage (e.g., a power voltage) according to program data. During a read operation, the register 32 may detect data from a memory cell that is selected through a bit line. Although not illustrated in FIG. 2, the remaining pairs of bit lines are respectively connected to corresponding registers with the same structure like FIG. 2.
As illustrated above, flash memories may be erased and programmed in large blocks. Assuming that one word line includes two pages (an even page and an odd page), each of the memory cells stores 2 bit data, and one memory block includes 32 word lines, one memory block includes 128 pages (32WL*2P*2B). Here, WL, P, and B represent a word line, a page, and a bit, respectively.
A row address includes a block address for selecting memory blocks and a page address for selecting pages in the selected memory block. For example, a 7 bit address (hereinafter, referred to as a first row address) may be used to select 128 pages. A 10 bit address (hereinafter, referred to as a second row address) may be used to select 1024 memory blocks. Address coding is used to select all pages in one memory block, and then pages in the memory block.
For example, as illustrated in FIG. 3A, a 7 bit address A12 to A18 is used to select 128 pages at each memory block, and a plurality of address bits A19 to Ai are used to select memory blocks. The number of address bits to select the memory blocks is determined according to the number of the memory blocks. When the 7 bit address is 0000000, the first page OP in the selected memory block is selected. When the 7 bit address is 1111111, the last page 127P in the selected memory block is selected. Thus, an external address provided may be mapped to a physical address of the flash memory device.
However, a problem may arise when storing 3-bit (2N+1-bit) data at each cell instead of storing 2 bit (2N-bit) data at each cell. When storing the 3-bit data at each cell, since 32 word lines, and odd and even bit lines are provided, one memory block includes 192 pages (32WL*2P*3B).
When storing the 3-bit data at each cell, as illustrated in FIG. 3B, since one memory block includes 192 pages, the memory block may not be uniquely divided into a page address and a block address. An 8-bit address is required to select 192 pages. However, 256 pages can be substantially selected by an 8-bit address. For that reason, there are pages that are selected by the 8-bit address, but are not substantially allocated to each memory block.
This problem may be illustrated by comparing FIGS. 3A and 3B. When the flash memory device stores 2-bit data at each cell, as illustrated in FIG. 3A, a page address selecting the first/last pages of the first memory block BLK0 is identical to a page address for selecting the first/last page of a second or another memory block. In contrast, when the flash memory device stores 3-bit data at each cell, as illustrated in FIG. 3B, a page address selecting the first/last pages of the first memory block BLK0 is different from a page address for selecting the first/last page of a second or another memory block. This means that a row address does not convert into a page address and a block address of a flash memory device. That is, when storing 3-bit data at each cell, a block address mapped into memory blocks may not be distinguishable from a page address. Thus, a memory controller controlling a flash memory device may require an address conversion table for converting a row address into a block address and a page address of the flash memory device illustrated in FIG. 3B.